1. Field of the Invention
The present invention relates to the design of integrated circuits. More specifically, the present invention relates to a method and an apparatus for grouping flip-flops by timing during the design of an integrated circuit.
2. Related Art
The process of designing integrated circuits, particularly central processing units, involves a large number of operations. During the design process, hundreds of millions of transistors and associated signal lines may need to be incorporated into a working layout. While many of these operations can be automated, some operations remain largely manual operations, and are hence time-consuming and prone to human error.
One of these manual operations involves placing flip-flops between circuit blocks of the integrated circuit. Current methods for placing flip-flops do not associate flip-flops with metal layers in the integrated circuit.
Integrated circuits typically have several metal layers, wherein each layer has a different width and spacing. The length, width, and spacing of the metal layer wires interconnecting the various devices and blocks on the integrated circuit all affect the RC parasitics and, thus, the timing of the signals. Hence, associating flip-flops with specific metal layers is critical for timing in the circuit and therefore affects performance of the circuit. Unfortunately, at the present moment, the process of determining the correct metal layer for a flip-flop is a manual operation, which is time-consuming and prone to error.
Hence, what is needed is a method and an apparatus for associating flip-flops with metal layers without the problems described above.